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Silicon Wafer
SOI Wafer
In order to improve the integration and speed of integrated circuits, the size of devices must be reduced to reduce the power consumption. However, when the size of the device is reduced to the submicron range, the conventional structure is not suitable, which leads to the development of SOI (silicon on insulator or semiconductor on insulator) structure, that is, the device is made on the silicon single crystal layer grown on the insulating substrate. SOI structure was proposed for submicron CMOS devices to replace the conventional structure which is not suitable for the requirements and the applied SOS structure (SOS can be regarded as a form of SOI). However, SOI structure soon became a new way to realize high-speed integrated circuit and three-dimensional integrated circuit (but not all SOI structures can be used for three-dimensional integrated circuit), which is a current semiconductor material research hotspot issues.
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Product Detail
 Diameter 4"  5"  6"  8" 
Device Layer Dopant Boron, Phos, Arsenic, Antimony, Undoped
Orientation  <100>, <111>
Type SIMOX, BESOI, Simbond, Smart-cut
Resistivity  0.001-20000 Ohm-cm
Thickness (um) 0.2-150
The Uniformity <5%
BOX Layer   Thickness (um) 0.4-3
Uniformity <2.5%
Substrate   Orientation  <100>, <111>
Type/Dopant P Type/Boron , N Type/Phos,  N Type/As, N Type/Sb
Thickness (um) 300-725
Resistivity  0.001-20000 Ohm-cm
Surface Finished P/P, P/E
Particle <10@.0.3um

Silicon on Insulator
 
Silicon on Insulator (SOI) is a technology that bonds an active wafer to a handle wafer with an oxide layer in between.
 
PLUTO offers a wide range of SOI products, suitable for a variety of applications.
 
Silicon on Insulator is commonly used in MEMS, Automotive and applications where high temperature tolerance and high noise immunity are key requirements.
 
Silicon on Insulator wafers are composed of a three-layer material stack: Active layer of prime quality silicon (DEVICE LAYER) over a buried layer(BOX) of electrically insulating silicon dioxide, over a bulk silicon support wafer (HANDLE).
 
 
SOI Technology
 
In order to improve the integration and speed of integrated circuits, the size of devices must be reduced to reduce the power consumption. However, when the size of the device is reduced to the submicron range, the conventional structure is not suitable, which leads to the development of SOI (silicon on insulator or semiconductor on insulator) structure, that is, the device is made on the silicon single crystal layer grown on the insulating substrate. SOI structure was proposed for submicron CMOS devices to replace the conventional structure which is not suitable for the requirements and the applied SOS structure (SOS can be regarded as a form of SOI). However, SOI structure soon became a new way to realize high-speed integrated circuit and three-dimensional integrated circuit (but not all SOI structures can be used for three-dimensional integrated circuit), which is a current semiconductor material research hotspot issues.
 
The advantages of SOI structure can be summarized as follows:
 
(1) due to its dielectric isolation and small parasitic capacitance, it is particularly advantageous for high-speed and high integration IC circuits
 
(2) due to the isolation of medium, the noise is reduced and the radiation resistance of circuit and device is improved.
 
(3) the latch-u-up problem of CMOS circuits is suppressed.
 
Compared with SOS, the integrity of SOI material is much better than SOS, and SOI structure is widely used in CMOS circuits, which can reduce the number of masking, do not need isolation and diffusion, simplify the circuit layout, and improve the integration. The coefficient of thermal expansion of Si and Al2O3 in SOS does not match, and there is compressive stress in silicon layer. In addition, the power consumption and substrate cost of SO1 are much lower than that of SOS, and SOS does not realize the function of three-dimensional device structure.
 
From the current situation, some SOI technologies have initially become practical. As long as the process and material quality problems can be further overcome, there is no problem in the practical application. Some SOI technologies can be used to manufacture SOI structural materials for three-dimensional IC, and there are many methods. The following briefly introduces several main methods:
 
1. Melting transverse growth
 
The basic process of this method is to form a layer of so film on the silicon substrate, and then the polycrystalline or amorphous silicon deposited by polycrystalline or amorphous silicon on the film will melt locally, while the moving melting zone will melt the polycrystalline or amorphous silicon before the melting zone, and the recrystallization will take place behind the melting zone. This method can be divided into four kinds due to the different heat sources of forming the melting zone: ①laser beam melting recrystallization; ②electron beam melting recrystallization; ③graphite strip heating transverse seed recrystallization; and light melting recrystallization. Because of the different heating methods, the equipment and the specific process are very different, the results are different, each has its own advantages and disadvantages. In the early stage, this kind of method was studied actively.
 
2. CVD lateral growth
 
CVD lateral growth is a lateral epitaxial growth method on SiO2, which is called ELO (epitaxial lateral over growth) method for short. It is developed in the choice of extension, and it is highly valued by people. This is because the silicon epitaxial growth technology is relatively mature, the processing temperature is low (1050 ~ 1150 ℃), far lower than the Si melting temperature, which will not cause serious redistribution of substrate impurities, and it is expected to be used in the fabrication of 3D IC.
 
The basic process of this method is to use photolithography technology to open the substrate window on the SiO2 film, epitaxial grow silicon at the window, and inhibit the silicon nucleation on the SiO2 surface. When the window area is full of silicon, the lateral epitaxy can be carried out with a large ratio of the growth rate of transverse to longitudinal. The key of this method is how to inhibit the nucleation on SiO2. At present, the growth / corrosion process is used to solve this problem, that is, stop the growth after each growth period, and introduce HCl gas phase corrosion to remove the silicon deposited on SiO2. Then the second growth / corrosion was carried out until the window was full, and the growth / corrosion continued to be repeated for lateral growth. Finally, the silicon film was connected into a piece and grew to the required thickness, and the electrical properties and device properties of the obtained SOI structure were close to those of conventional epitaxial growth under the same conditions. At present, the polycrystalline nucleus on the SiO2 film can not be completely removed, which affects the quality of ELO film. In addition, the width of lateral growth is not very wide.
 
3. SOI structure formed by oxygen ion implantation
 
This method is also called SIMOX (separation by implantable oxygen). It is a method of forming SiO2 buried layer with stoichiometric ratio by oxygen ion implantation. The amount of oxygen ion implanted is about 1.2 ~ 1.8 × 10 / cm2. The depth of buried layer is related to the injected energy. If the depth of buried layer is 0.5 μ m, the injected energy is about 500kev. If the depth is 1um, 1MeV is needed

 
 
In order to obtain the abrupt Si-SiO2 interface, the dose of oxygen ion implantation is usually over 1.8 × 1018 / cm2. When the dose is insufficient, twin layer will appear at the upper interface. Fig. 5-22 is a schematic diagram of the interface state between the injection dose and the silicon dioxide.
 
After oxygen ion implantation, annealing heat treatment must be carried out at high temperature to form SiO2 and eliminate lattice damage. The treatment temperature is 1150 ~ 1250 ℃, and the time is 2H. Before annealing, the deposition of a layer of SiO2 on the surface of silicon wafer can improve the annealing effect and reduce the surface defects.
 
SIMOX method is simple and easy to operate, and it can get good single crystal layer which is completely compatible with conventional silicon device technology. It can be said that it is the most attractive SOI technology, but the disadvantage is that it can not be made into three-dimensional devices.
 
4. Wafer surface bonding
 
In this method, two silicon wafers are bonded together through the SiO2 layer on the surface, and then the back surface is thinned by corrosion and other methods to obtain SOI structure. One of the methods is to oxidize one of the two polishing pieces of silicon to form a SiO2 film, stick the other piece on it, heat treat in an oxygen atmosphere, and bond together through the polymerization of the silicon oxygen bond at the interface during the oxidation heat treatment. This method is relatively simple, but it is difficult to reduce the thickness. In addition, it requires high flatness of the film, otherwise the whole interface is difficult to fully fit. This method is developing rapidly.
 
SOI technology has been studied for many years, and some results have been achieved. Many advanced industrial countries have invested a lot of efforts in the research. Once the breakthrough progress is achieved, its application prospect is very broad.

 
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